The described embodiments relate to a power supply noise analysis model creation method, a power supply noise analysis model creation apparatus and a power supply noise analysis model creation program.
A power supply and ground layer analysis model is used to analyze power supply noise caused on a circuit board such as a PCB (Printed-Circuit Board; hereinafter the same), MCM (Multi-Chip Module) or LSI (Large Scale Integrated circuit; hereinafter the same) package.
To analyze the electrical characteristics and the circuit operation of the power supply and the ground layer of a circuit board, an analysis model is created from the design data of the circuit board, and the analysis model is solved utilizing a circuit simulator. SPICE (Simulation Program with Integrated Circuit Emphasis) is a typical circuit simulator.
In a surface mount type LSI with part pins arranged on the LSI bottom in a grid-like fashion, which is called PGA (Pin Grid Array), LGA (Land Grid Array) or BGA (Ball Grid Array), drawing vias from surface mount pads are also arranged on the grid. Therefore, on the circuit board, the power supply or the ground plane provided on an area where an LSI is to be mounted, may be provided with an area without a conductor in a manner that a passing via is surrounded by the area. Thereby avoiding a short circuit with a via in a different net. This area is referred to as a via clearance hole. It is conceivable that, if it is not possible to reflect the shape of the via clearance hole when creating the analysis model, the accuracy of an analysis result deteriorates.
(for example, Japanese Patent Laid-Open No. 2006-209590, Japanese Patent Laid-Open No. 2002-368116, Japanese Patent Laid-Open No. 2003-141205, Japanese Patent Laid-Open No. 2004-334654 and Japanese Patent Laid-Open No. 2004-334618).